component neorv32_SystemTop_axi4lite generic ( -- ------------------------------------------------------------ -- Configuration Generics -- -- ------------------------------------------------------------ -- General -- CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz INT_BOOTLOADER_EN : boolean := false; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit) -- On-Chip Debugger (OCD) -- ON_CHIP_DEBUGGER_EN : boolean := false; -- implement on-chip debugger -- RISC-V CPU Extensions -- CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension? CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit-manipulation extension? CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension? CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension? CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT reg!) CPU_EXTENSION_RISCV_Zicsr : boolean := false; -- implement CSR system? CPU_EXTENSION_RISCV_Zicntr : boolean := false; -- implement base counters? CPU_EXTENSION_RISCV_Zihpm : boolean := false; -- implement hardware performance monitors? CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.? CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension? CPU_EXTENSION_RISCV_Zxcfu : boolean := false; -- implement custom (instr.) functions unit? -- Extension Options -- FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64) -- Physical Memory Protection (PMP) -- PMP_NUM_REGIONS : natural := 0; -- number of regions (0..16) PMP_MIN_GRANULARITY : natural := 4; -- minimal region granularity in bytes, has to be a power of 2, min 4 bytes -- Hardware Performance Monitors (HPM) -- HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29) HPM_CNT_WIDTH : natural := 40; -- total size of HPM counters (0..64) -- Internal Instruction memory -- MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes -- Internal Data memory -- MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes -- Internal Cache memory -- ICACHE_EN : boolean := false; -- implement instruction cache ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2 ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2 ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2 -- External Interrupts Controller (XIRQ) -- XIRQ_NUM_CH : natural := 0; -- number of external IRQ channels (0..32) XIRQ_TRIGGER_TYPE : std_logic_vector(31 downto 0) := x"FFFFFFFF"; -- trigger type: 0=level, 1=edge XIRQ_TRIGGER_POLARITY : std_logic_vector(31 downto 0) := x"FFFFFFFF"; -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge -- Processor peripherals -- IO_GPIO_EN : boolean := false; -- implement general purpose input/output port unit (GPIO)? IO_MTIME_EN : boolean := false; -- implement machine system timer (MTIME)? IO_UART0_EN : boolean := false; -- implement primary universal asynchronous receiver/transmitter (UART0)? IO_UART0_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1 IO_UART0_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two, min 1 IO_UART1_EN : boolean := false; -- implement secondary universal asynchronous receiver/transmitter (UART1)? IO_UART1_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1 IO_UART1_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two, min 1 IO_SPI_EN : boolean := false; -- implement serial peripheral interface (SPI)? IO_TWI_EN : boolean := false; -- implement two-wire interface (TWI)? IO_PWM_NUM_CH : natural := 4; -- number of PWM channels to implement (0..60); 0 = disabled IO_WDT_EN : boolean := false; -- implement watch dog timer (WDT)? IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)? IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)? IO_CFS_CONFIG : std_logic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits IO_NEOLED_EN : boolean := false; -- implement NeoPixel-compatible smart LED interface (NEOLED)? IO_NEOLED_TX_FIFO : natural := 1; -- NEOLED TX FIFO depth, 1..32k, has to be a power of two IO_GPTMR_EN : boolean := false; -- implement general purpose timer (GPTMR)? IO_XIP_EN : boolean := false -- implement execute in place module (XIP)? ); port ( -- ------------------------------------------------------------ -- AXI4-Lite-Compatible Master Interface -- -- ------------------------------------------------------------ -- Clock and Reset -- m_axi_aclk : in std_logic; m_axi_aresetn : in std_logic; -- Write Address Channel -- m_axi_awaddr : out std_logic_vector(31 downto 0); m_axi_awprot : out std_logic_vector(2 downto 0); m_axi_awvalid : out std_logic; m_axi_awready : in std_logic; -- Write Data Channel -- m_axi_wdata : out std_logic_vector(31 downto 0); m_axi_wstrb : out std_logic_vector(3 downto 0); m_axi_wvalid : out std_logic; m_axi_wready : in std_logic; -- Read Address Channel -- m_axi_araddr : out std_logic_vector(31 downto 0); m_axi_arprot : out std_logic_vector(2 downto 0); m_axi_arvalid : out std_logic; m_axi_arready : in std_logic; -- Read Data Channel -- m_axi_rdata : in std_logic_vector(31 downto 0); m_axi_rresp : in std_logic_vector(1 downto 0); m_axi_rvalid : in std_logic; m_axi_rready : out std_logic; -- Write Response Channel -- m_axi_bresp : in std_logic_vector(1 downto 0); m_axi_bvalid : in std_logic; m_axi_bready : out std_logic; -- ------------------------------------------------------------ -- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) -- -- ------------------------------------------------------------ jtag_trst_i : in std_logic := '0'; -- low-active TAP reset (optional) jtag_tck_i : in std_logic := '0'; -- serial clock jtag_tdi_i : in std_logic := '0'; -- serial data input jtag_tdo_o : out std_logic; -- serial data output jtag_tms_i : in std_logic := '0'; -- mode select -- ------------------------------------------------------------ -- Processor IO -- -- ------------------------------------------------------------ -- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) -- xip_csn_o : out std_logic; -- chip-select, low-active xip_clk_o : out std_logic; -- serial clock xip_sdi_i : in std_logic := 'L'; -- device data input xip_sdo_o : out std_logic; -- controller data output -- GPIO (available if IO_GPIO_EN = true) -- gpio_o : out std_logic_vector(63 downto 0); -- parallel output gpio_i : in std_logic_vector(63 downto 0) := (others => '0'); -- parallel input -- primary UART0 (available if IO_UART0_EN = true) -- uart0_txd_o : out std_logic; -- UART0 send data uart0_rxd_i : in std_logic := '0'; -- UART0 receive data uart0_rts_o : out std_logic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional uart0_cts_i : in std_logic := '0'; -- hw flow control: UART0.TX allowed to transmit, low-active, optional -- secondary UART1 (available if IO_UART1_EN = true) -- uart1_txd_o : out std_logic; -- UART1 send data uart1_rxd_i : in std_logic := '0'; -- UART1 receive data uart1_rts_o : out std_logic; -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional uart1_cts_i : in std_logic := '0'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional -- SPI (available if IO_SPI_EN = true) -- spi_sck_o : out std_logic; -- SPI serial clock spi_sdo_o : out std_logic; -- controller data out, peripheral data in spi_sdi_i : in std_logic := '0'; -- controller data in, peripheral data out spi_csn_o : out std_logic_vector(07 downto 0); -- SPI CS -- TWI (available if IO_TWI_EN = true) -- twi_sda_io : inout std_logic; -- twi serial data line twi_scl_io : inout std_logic; -- twi serial clock line -- PWM (available if IO_PWM_NUM_CH > 0) -- pwm_o : out std_logic_vector(59 downto 0); -- pwm channels -- Custom Functions Subsystem IO (available if IO_CFS_EN = true) -- cfs_in_i : in std_logic_vector(IO_CFS_IN_SIZE-1 downto 0) := (others => '0'); -- custom inputs cfs_out_o : out std_logic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom outputs -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) -- neoled_o : out std_logic; -- async serial data line -- External platform interrupts (available if XIRQ_NUM_CH > 0) -- xirq_i : in std_logic_vector(31 downto 0) := (others => '0'); -- IRQ channels -- CPU Interrupts -- msw_irq_i : in std_logic := '0'; -- machine software interrupt mext_irq_i : in std_logic := '0' -- machine external interrupt ); end component;