# Command I ran and output:
$ screen /dev/tty.usbserial-B0010NHK 115200
# -----------------------------------------------------------------------------------------------------

F0: 102B 0000
F3: 1006 0033 [0200]
F3: 4001 00E0 [0200]
F3: 0000 0000
V0: 0000 0000 [0001]
00: 0000 0000
BP: 0C00 0241 [0000]
G0: 1190 0000
EC: 0000 0000 [0001]
T0: 0000 0156 [000F]
Jump to BL

NOTICE:  BL2: v2.6(release):ea4af38bb-dirty
NOTICE:  BL2: Built : 10:45:31, Jul  8 2022
Pll init start...
INFRA_BUS_DCM_CTRL 5f7fe0
before: WDT_SWSYSRST = 0x8000
after: WDT_SWSYSRST = 0x9000
Pll init Done!
[PWRAP] si_en_sel = 0, si_ck_sel = 0, si_sample_ctrl = 0, rdata = 96a9
[PWRAP] si_en_sel = 0, si_ck_sel = 1, si_sample_ctrl = 20, rdata = 5aa5, Pass
[PWRAP] InitSiStrobe (7, 7, 4804) Data Boundary Is Found !!
[PWRAP] SI Strobe Calibration For PMIC 0 Done, (40, 7)
[PWRAP] Read Test pass, return_value=0x0
[PWRAP] Write Test pass
[PWRAP] RECORD_CMD0:  0x0 (Last one command addr)
[PWRAP] RECORD_WDATA0:0x0 (Last one command wdata)
[PWRAP] RECORD_CMD1:  0x0 (Last second command addr)
[PWRAP] RECORD_WDATA1:0x0 (Last second command wdata)
[PWRAP] RECORD_CMD2:  0x0 (Last third command addr)
[PWRAP] RECORD_WDATA2:0x0 (Last third command wdata)
[I2C] Init done
[PMIC]Start
[PMIC]MT6357 CHIP Code = 0x57, mrv=1
[PMIC]POWER_HOLD :0x1
[PMIC]TOP_RST_STATUS[0x152]=0x0
[PMIC]PONSTS[0xc]=0x4
[PMIC]POFFSTS[0xe]=0x0
[PMIC]PGSTATUS0[0x14]=0xfffe
[PMIC]PSOCSTATUS[0x16]=0x0
[PMIC]BUCK_OC_SDN_STATUS[0x1434]=0x0
[PMIC]BUCK_OC_SDN_EN[0x1444]=0x1d1f
[PMIC]THERMALSTATUS[0x18]=0x0
[PMIC]STRUP_CON4[0xa1c]=0x0
[PMIC]TOP_RST_MISC[0x14c]=0x200
[PMIC]TOP_CLK_TRIM[0x38e]=0x6ac0
latch VPROC 800000 uV
latch VSRAM_PROC 900000 uV
latch VSRAM_OTHERS 900000 uV
latch VCORE 800000 uV
latch VMODEM 800000 uV
[pmic_check_rst] PORSTB
[PMIC]just_rst = 0
No EFUSE SW Load
[PMIC]pmic_wdt_set Reg[0x14c]=0x221
[rt5738_driver_probe]
[update_rt5738_chip_id] 0x0, 0x0, 0x0
[rt5738_hw_component_detect] ret 1, PGOOD 0x1
[rt5738_hw_component_detect] mt6691_vdd2(0) exist = 1, Chip ID = 0
mt6691_vdd2_hw_init
[0x0]=0xa5 [0x1]=0xa5 [0x2]=0x92 [0x3]=0x0 [0x4]=0x0 [0x5]=0x81 [0x6]=0x63
[rt5738_driver_probe] PL g_rt5738_0_hw_exist=1, g_rt5738_driver_ready=1
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[update_rt5738_chip_id] 0x0, 0x0, 0x0
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[rt5738_hw_component_detect] ret 0, PGOOD 0x0
[rt5738_hw_component_detect] mt6691_vddq(1) exist = 0, Chip ID = 0
[rt5738_driver_probe] PL mt6691_vddq is not exist
[I2C] id=0,addr: 54, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a8,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[I2C] id=0,addr: 54, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a8,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[update_rt5738_chip_id] 0x0, 0x0, 0x0
[I2C] id=0,addr: 54, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a8,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[rt5738_hw_component_detect] ret 0, PGOOD 0x0
[rt5738_hw_component_detect] ma5748_vdd(2) exist = 0, Chip ID = 0
[rt5738_driver_probe] PL ma5748_vdd is not exist
[hl7593_driver_probe]
[hl7593_read_interface] Reg[3]=0x0
[hl7593_read_interface] val=0x0
[hl7593_read_interface] Reg[4]=0x0
[hl7593_read_interface] val=0x0
[update_hl7593_chip_id] 0x0, 0x0, 0x0
[hl7593_read_interface] Reg[5]=0x81
[hl7593_read_interface] val=0x1
PGOOD = 1, chip_id = 0
[hl7593_hw_component_detect] exist = 0, Chip ID = 0
[hl7593_driver_probe] PL hl7593_vdd2 is not exist
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[hl7593_read_interface] Reg[3]=0x3
[hl7593_read_interface] val=0x3
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[hl7593_read_interface] Reg[4]=0x4
[hl7593_read_interface] val=0x4
[update_hl7593_chip_id] 0x3, 0x4, 0x304
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[hl7593_read_interface] Reg[5]=0x5
[hl7593_read_interface] val=0x0
PGOOD = 0, chip_id = 772
[hl7593_hw_component_detect] exist = 0, Chip ID = 304
[hl7593_driver_probe] PL hl7593_vddq is not exist
[fan53526_driver_probe]
[I2C] id=0,addr: 60, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=c0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[I2C] id=0,addr: 60, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=c0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[update_fan53526_chip_id] 0x3, 0x4, 0x304
[I2C] id=0,addr: 60, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=c0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[fan53526_hw_component_detect] exist = 0, Chip ID = 304
[fan53526_driver_probe] PL fan53526_vdd2 is not exist
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[update_fan53526_chip_id] 0x3, 0x4, 0x304
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[fan53526_hw_component_detect] exist = 0, Chip ID = 304
[fan53526_driver_probe] PL fan53526_vddq is not exist
register vs1 OK
register vmodem OK
register vcore OK
register vproc OK
register vpa OK
register vsram_others OK
register vsram_proc OK
register vdram OK
register vfe28 OK
register vefuse OK
[PMIC]Init done
init_dram:1723: init_dram Starting
Fanning new driver,dram type 3
[MT6357] 1 2,25
[RankNumberDetection] 2

[CH0][RK0][1600][CBT] Best CA Vref 10, Window Min 59 at CA4, Window Sum 358

[CH0][RK1][1600][CBT] Best CA Vref 8, Window Min 59 at CA4, Window Sum 361

[CH0][RK0][1600][TX] Best Vref 12, Window Min 27 at DQ1, Window Sum 440

[CH0][RK0][1600][RX] Best Vref 28, Window Min 56 at DQ7, Window Sum 918
Byte0 end_step=17  best_step=14 Final TX OE(2T, 0.5T) = (1, 6)
Byte1 end_step=17  best_step=14 Final TX OE(2T, 0.5T) = (1, 6)

[CH0][RK1][1600][TX] Best Vref 15, Window Min 27 at DQ1, Window Sum 443
Byte0 end_step=17  best_step=14 Final TX OE(2T, 0.5T) = (1, 6)
Byte1 end_step=17  best_step=14 Final TX OE(2T, 0.5T) = (1, 6)

[CH1][RK0][1600][CBT] Best CA Vref 8, Window Min 56 at CA4, Window Sum 352

[CH1][RK1][1600][CBT] Best CA Vref 8, Window Min 56 at CA4, Window Sum 349

[CH1][RK0][1600][TX] Best Vref 11, Window Min 27 at DQ0, Window Sum 444

[CH1][RK0][1600][RX] Best Vref 28, Window Min 54 at DQ8, Window Sum 908
Byte0 end_step=17  best_step=14 Final TX OE(2T, 0.5T) = (1, 6)
Byte1 end_step=17  best_step=14 Final TX OE(2T, 0.5T) = (1, 6)

[CH1][RK1][1600][TX] Best Vref 16, Window Min 27 at DQ6, Window Sum 442
Byte0 end_step=17  best_step=14 Final TX OE(2T, 0.5T) = (1, 6)
Byte1 end_step=17  best_step=14 Final TX OE(2T, 0.5T) = (1, 6)


[Calibration Summary] Freqency 800
CH 0, Rank 0
All Pass.
CH 0, Rank 1
All Pass.
CH 1, Rank 0
All Pass.
CH 1, Rank 1
All Pass.
CH0, RK0, Rank Size: 0x40000000.
CH1, RK0, Rank Size: 0x40000000.
CH0, RK1, Rank Size: 0x40000000.
CH1, RK1, Rank Size: 0x40000000.
[MT6357] 1 2,37

[CH0][RK0][2666][CBT] Best CA Vref 8, Window Min 51 at CA4, Window Sum 318

[CH0][RK1][2666][CBT] Best CA Vref 8, Window Min 51 at CA4, Window Sum 323

[CH0][RK0][2666][TX] Best Vref 10, Window Min 25 at DQ12, Window Sum 422

[CH0][RK0][2666][RX] Best Vref 13, Window Min 36 at DQ0, Window Sum 610
Byte0 end_step=26  best_step=23 Final TX OE(2T, 0.5T) = (2, 7)
Byte1 end_step=25  best_step=22 Final TX OE(2T, 0.5T) = (2, 6)

[CH0][RK1][2666][TX] Best Vref 10, Window Min 25 at DQ6, Window Sum 426
Byte0 end_step=26  best_step=23 Final TX OE(2T, 0.5T) = (2, 7)
Byte1 end_step=25  best_step=22 Final TX OE(2T, 0.5T) = (2, 6)

[CH1][RK0][2666][CBT] Best CA Vref 8, Window Min 50 at CA4, Window Sum 324

[CH1][RK1][2666][CBT] Best CA Vref 8, Window Min 50 at CA4, Window Sum 322

[CH1][RK0][2666][TX] Best Vref 10, Window Min 24 at DQ13, Window Sum 417

[CH1][RK0][2666][RX] Best Vref 12, Window Min 36 at DQ6, Window Sum 599
Byte0 end_step=26  best_step=23 Final TX OE(2T, 0.5T) = (2, 7)
Byte1 end_step=26  best_step=23 Final TX OE(2T, 0.5T) = (2, 7)

[CH1][RK1][2666][TX] Best Vref 10, Window Min 24 at DQ6, Window Sum 415
Byte0 end_step=26  best_step=23 Final TX OE(2T, 0.5T) = (2, 7)
Byte1 end_step=26  best_step=23 Final TX OE(2T, 0.5T) = (2, 7)


[Calibration Summary] Freqency 1333
CH 0, Rank 0
All Pass.
CH 0, Rank 1
All Pass.
CH 1, Rank 0
All Pass.
CH 1, Rank 1
All Pass.
[MT6357] 1 2,45

[CH0][RK0][3200][CBT] Best CA Vref 8, Window Min 50 at CA4, Window Sum 313

[CH0][RK1][3200][CBT] Best CA Vref 8, Window Min 50 at CA4, Window Sum 320

[CH0][RK0][3200][TX] Best Vref 10, Window Min 20 at DQ13, Window Sum 368

[CH0][RK0][3200][RX] Best Vref 12, Window Min 32 at DQ4, Window Sum 550
Byte0 end_step=30  best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
Byte1 end_step=30  best_step=27 Final TX OE(2T, 0.5T) = (3, 3)

[CH0][RK1][3200][TX] Best Vref 10, Window Min 20 at DQ13, Window Sum 372
Byte0 end_step=30  best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
Byte1 end_step=30  best_step=27 Final TX OE(2T, 0.5T) = (3, 3)

[CH1][RK0][3200][CBT] Best CA Vref 8, Window Min 50 at CA4, Window Sum 330

[CH1][RK1][3200][CBT] Best CA Vref 8, Window Min 50 at CA4, Window Sum 329

[CH1][RK0][3200][TX] Best Vref 12, Window Min 22 at DQ3, Window Sum 364

[CH1][RK0][3200][RX] Best Vref 12, Window Min 31 at DQ3, Window Sum 515
Byte0 end_step=30  best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
Byte1 end_step=30  best_step=27 Final TX OE(2T, 0.5T) = (3, 3)

[CH1][RK1][3200][TX] Best Vref 12, Window Min 21 at DQ7, Window Sum 363
Byte0 end_step=30  best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
Byte1 end_step=30  best_step=27 Final TX OE(2T, 0.5T) = (3, 3)


[Calibration Summary] Freqency 1600
CH 0, Rank 0
All Pass.
CH 0, Rank 1
All Pass.
CH 1, Rank 0
All Pass.
CH 1, Rank 1
All Pass.
final ma_type:2
final ma_type:2


[DRAM_CHECK] result = 0

[switch_dramc_voltage_to_auto_mode]switch dram voltage to auto mode done!!!

base init: MT8365 platform
NOTICE:  BL2: Booting BL31
NOTICE:  BL31: v2.6(release):ea4af38bb-dirty
NOTICE:  BL31: Built : 10:45:31, Jul  8 2022
...
��*JJj /t��83>/���(
                  "���&�JJKCFJ7���8����'8����V���&VW�w(�W?      q'��8&�C�w�     n!Jb�)()        �
                                                                                                 "��B�)
                                                                                                       N+�+)�9"�v��wJjW?.�g�6   "��*�7
                                                                                                                                      c
                                                                                                                                       ++�O�B0�],R "�g*2%E+:��v��w(W?wn�W�>֠C�8���wJ�w2>�mBF� �/l0"�OFJ�wSGJ������V����:F(
ʌ�&JF��NJB�F����ʆ���F�JJJʆ�f҆�����G�NJ����v�OJwqG�wB��ֆ����������B�R�����J�jB����jV���gτ��O��^�z�����C�J�B��O����Kf����C�kzB���~B��ϬBÏ��v�w�B��B��[[������ZC����ZC��j������ƬB[p��R��ެ�Z�O��JʴB���N�Z�Z�ެ`ZwP��J�Z�O��N�Z��ެ�ZwP��J�Z����N�ZB����      ������Ά������G�o��B�����B��Ʀ��O����[Kf����[r~�B�_��j��������    �������������F����g��NjG��ʝK�jBg�^�G��Fʎ��z�ڥn�jr��Oz�����z�����B�����z���b�O^�Bw����ƴ������G������wB�����z������KZ�V��BB����J��^�J���VD�����[B�V������&J��KJ����R~��Z�BS���      ���[B~fB����[B~�B����Kc~&BK��KB~fB����GV"B[��[C������[C�����Ƅ�V��׆�������������FkS�"B�׆�������dž��FvB��rPoB�ˬ2�B��������b��v�����w�����Jk��B����������^����^��>ZK�O�~B���j�o�z^P~���z��z�W�j�J����Nj���B�K�_W���ZsK�_W��R��j����&jKFNWJk�[b_�B��o��BkFnWJK�[b_�BKFNWJk�[b_�B�����B����B�k���{�B����O�K�B����O�K�Bۯ���O��B����O��B����O�K�B����O�K�B����O�k�B����O��B�k�_W���B����O�j�B���̞OB���B�r��B������B���B�Z�B�n�Bv�~�����N��N�C��BC_v����b���Bj����'��Bk�B�����SqF���B�_�����?J��bR_�BO�kB�����BO�gJ�BO���w��Bs����BO����B�kN�B�kN�n3z�kN��B�kN�JN�B�kN�nBO�ƽ���B�G��f�j����B������B����B�G���B����f~z�����B������B�G���B�Kf��w��B�Kf��~z�Kf�����B�Kf�N�NNJ�B�Kf��jBSBP�B�k��B�Kf��~r�Kf�����B�Kf��R��B�����S��vB�j�^B�B���~o�B������B����J��Bj����B�k���Bsk����׾�B��O���k߯K�B������gq���B�[F�>r���B���G��g����B��Ƈ��B�b�K�KjB�����Gk����B�����B[�Z����B��B������B��O~B����B��j�B��J�_W���Bsk���{�B��WK��n��B��K_W���B���N_W���B��K��n��B�KN���B�KNV�����BGJ��J�B�J���B��vBGo��jB�k�^J����B�k�^K���c��k�^J����B�k�^K����B��_N�w�B��_N_W���B��_N�w�B��_N_W���B�wN��W�B��wN��n��B��wK��W�B��wK��n��B�J��J�B�[v�G�N�B�[v����zGJ�W���B�[vJ�J�BGJ��J�B�[vJ�J�BGJ�����GsBGJ��^��dž��B�[vVGB�^B���B���zB�G��B�rr�jB�r�cgB��W���SƞjC[�z�W��ZoS{B�����B��Bb�B�r�SgB�vjSgB�FjSל�z�BoO��Ƨ�������w����������������Bڜ���B�����B�����BC�����OwVB������מ��FBڜ���B������OwVB����B����������OwVB������OwV������q�v�g$���b����R������k���R����[����C������Bj��B[BBBBB�B�BBp�O�����W�����Cj�j�J��O��B�vBBB���RB�B�BBp�J�������R�B��[����C��~�׭וJ��B[BBBBB�B�BBp�O�����W����Cj�jjJz W�KBBB�w��B�B�BBp�J�������R�B��[����C������וJ��BKBBBBB�B�BBp�O�����WǏ���Cj�jjJz[�ҿ�BB�BBB�w�zBB�BBB�p�J���8���zBB����&��J������OwVJ���J���z��?s��~�k��Z��vŭ�ŭ�Z������OwVŭ���Ư���k��k���΅b���k�����Kv{����Gv{�����G�Z�����g��������J�����J���
F0: 102B 0000
F3: 1006 0033 [0200]
F3: 4001 00E0 [0200]
F3: 0000 0000
V0: 0000 0000 [0001]
00: 0000 0000
BP: 0C00 0241 [0000]
G0: 1190 0000
EC: 0000 0000 [0001]
T0: 0000 010F [000F]
Jump to BL

NOTICE:  BL2: v2.6(release):ea4af38bb-dirty
NOTICE:  BL2: Built : 10:45:31, Jul  8 2022
Pll init start...
INFRA_BUS_DCM_CTRL 5f7fe0
before: WDT_SWSYSRST = 0x8000
after: WDT_SWSYSRST = 0x9000
Pll init Done!
[PWRAP] si_en_sel = 0, si_ck_sel = 0, si_sample_ctrl = 0, rdata = 96a9
[PWRAP] si_en_sel = 0, si_ck_sel = 1, si_sample_ctrl = 20, rdata = 5aa5, Pass
[PWRAP] InitSiStrobe (7, 7, 4804) Data Boundary Is Found !!
[PWRAP] SI Strobe Calibration For PMIC 0 Done, (40, 7)
[PWRAP] Read Test pass, return_value=0x0
[PWRAP] Write Test pass
[PWRAP] RECORD_CMD0:  0x14aa (Last one command addr)
[PWRAP] RECORD_WDATA0:0x2d (Last one command wdata)
[PWRAP] RECORD_CMD1:  0x19fa (Last second command addr)
[PWRAP] RECORD_WDATA1:0x3d (Last second command wdata)
[PWRAP] RECORD_CMD2:  0x19fa (Last third command addr)
[PWRAP] RECORD_WDATA2:0x39 (Last third command wdata)
[I2C] Init done
[PMIC]Start
[PMIC]MT6357 CHIP Code = 0x57, mrv=1
[PMIC]POWER_HOLD :0x1
[PMIC]TOP_RST_STATUS[0x152]=0x48
[PMIC]PONSTS[0xc]=0x0
[PMIC]POFFSTS[0xe]=0x400
[PMIC]PGSTATUS0[0x14]=0xfffe
[PMIC]PSOCSTATUS[0x16]=0x0
[PMIC]BUCK_OC_SDN_STATUS[0x1434]=0x0
[PMIC]BUCK_OC_SDN_EN[0x1444]=0x1d1f
[PMIC]THERMALSTATUS[0x18]=0x0
[PMIC]STRUP_CON4[0xa1c]=0x0
[PMIC]TOP_RST_MISC[0x14c]=0x204
[PMIC]TOP_CLK_TRIM[0x38e]=0x6ac0
latch VPROC 800000 uV
latch VSRAM_PROC 900000 uV
latch VSRAM_OTHERS 900000 uV
latch VCORE 800000 uV
latch VMODEM 500000 uV
[pmic_check_rst] DDLO_RSTB
[pmic_check_rst] AP Watchdog
[PMIC]just_rst = 0
No EFUSE SW Load
[PMIC]pmic_wdt_set Reg[0x14c]=0x225
[rt5738_driver_probe]
[update_rt5738_chip_id] 0x0, 0x0, 0x0
[rt5738_hw_component_detect] ret 1, PGOOD 0x1
[rt5738_hw_component_detect] mt6691_vdd2(0) exist = 1, Chip ID = 0
mt6691_vdd2_hw_init
[0x0]=0xa5 [0x1]=0xa5 [0x2]=0x92 [0x3]=0x0 [0x4]=0x0 [0x5]=0x81 [0x6]=0x63
[rt5738_driver_probe] PL g_rt5738_0_hw_exist=1, g_rt5738_driver_ready=1
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[update_rt5738_chip_id] 0x0, 0x0, 0x0
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[rt5738_hw_component_detect] ret 0, PGOOD 0x0
[rt5738_hw_component_detect] mt6691_vddq(1) exist = 0, Chip ID = 0
[rt5738_driver_probe] PL mt6691_vddq is not exist
[I2C] id=0,addr: 54, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a8,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[I2C] id=0,addr: 54, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a8,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[update_rt5738_chip_id] 0x0, 0x0, 0x0
[I2C] id=0,addr: 54, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a8,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[rt5738_hw_component_detect] ret 0, PGOOD 0x0
[rt5738_hw_component_detect] ma5748_vdd(2) exist = 0, Chip ID = 0
[rt5738_driver_probe] PL ma5748_vdd is not exist
[hl7593_driver_probe]
[hl7593_read_interface] Reg[3]=0x0
[hl7593_read_interface] val=0x0
[hl7593_read_interface] Reg[4]=0x0
[hl7593_read_interface] val=0x0
[update_hl7593_chip_id] 0x0, 0x0, 0x0
[hl7593_read_interface] Reg[5]=0x81
[hl7593_read_interface] val=0x1
PGOOD = 1, chip_id = 0
[hl7593_hw_component_detect] exist = 0, Chip ID = 0
[hl7593_driver_probe] PL hl7593_vdd2 is not exist
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[hl7593_read_interface] Reg[3]=0x3
[hl7593_read_interface] val=0x3
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[hl7593_read_interface] Reg[4]=0x4
[hl7593_read_interface] val=0x4
[update_hl7593_chip_id] 0x3, 0x4, 0x304
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[hl7593_read_interface] Reg[5]=0x5
[hl7593_read_interface] val=0x0
PGOOD = 0, chip_id = 772
[hl7593_hw_component_detect] exist = 0, Chip ID = 304
[hl7593_driver_probe] PL hl7593_vddq is not exist
[fan53526_driver_probe]
[I2C] id=0,addr: 60, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=c0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[I2C] id=0,addr: 60, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=c0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[update_fan53526_chip_id] 0x3, 0x4, 0x304
[I2C] id=0,addr: 60, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=c0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[fan53526_hw_component_detect] exist = 0, Chip ID = 304
[fan53526_driver_probe] PL fan53526_vdd2 is not exist
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[update_fan53526_chip_id] 0x3, 0x4, 0x304
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[fan53526_hw_component_detect] exist = 0, Chip ID = 304
[fan53526_driver_probe] PL fan53526_vddq is not exist
register vs1 OK
register vmodem OK
register vcore OK
register vproc OK
register vpa OK
register vsram_others OK
register vsram_proc OK
register vdram OK
register vfe28 OK
register vefuse OK
[PMIC]Init done
init_dram:1723: init_dram Starting
Fanning new driver,dram type 3
[MT6357] 1 2,25
[RankNumberDetection] 2

[CH0][RK0][1600][CBT] Best CA Vref 8, Window Min 59 at CA4, Window Sum 357

[CH0][RK1][1600][CBT] Best CA Vref 8, Window Min 59 at CA4, Window Sum 363

[CH0][RK0][1600][TX] Best Vref 14, Window Min 27 at DQ1, Window Sum 444

[CH0][RK0][1600][RX] Best Vref 30, Window Min 55 at DQ10, Window Sum 906
Byte0 end_step=17  best_step=14 Final TX OE(2T, 0.5T) = (1, 6)
Byte1 end_step=17  best_step=14 Final TX OE(2T, 0.5T) = (1, 6)

[CH0][RK1][1600][TX] Best Vref 13, Window Min 27 at DQ1, Window Sum 446
Byte0 end_step=17  best_step=14 Final TX OE(2T, 0.5T) = (1, 6)
Byte1 end_step=17  best_step=14 Final TX OE(2T, 0.5T) = (1, 6)

[CH1][RK0][1600][CBT] Best CA Vref 8, Window Min 56 at CA4, Window Sum 351

[CH1][RK1][1600][CBT] Best CA Vref 8, Window Min 56 at CA4, Window Sum 349

[CH1][RK0][1600][TX] Best Vref 13, Window Min 27 at DQ0, Window Sum 439

[CH1][RK0][1600][RX] Best Vref 28, Window Min 53 at DQ8, Window Sum 900
Byte0 end_step=17  best_step=14 Final TX OE(2T, 0.5T) = (1, 6)
Byte1 end_step=17  best_step=14 Final TX OE(2T, 0.5T) = (1, 6)

[CH1][RK1][1600][TX] Best Vref 17, Window Min 27 at DQ4, Window Sum 441
Byte0 end_step=17  best_step=14 Final TX OE(2T, 0.5T) = (1, 6)
Byte1 end_step=17  best_step=14 Final TX OE(2T, 0.5T) = (1, 6)


[Calibration Summary] Freqency 800
CH 0, Rank 0
All Pass.
CH 0, Rank 1
All Pass.
CH 1, Rank 0
All Pass.
CH 1, Rank 1
All Pass.
CH0, RK0, Rank Size: 0x40000000.
CH1, RK0, Rank Size: 0x40000000.
CH0, RK1, Rank Size: 0x40000000.
CH1, RK1, Rank Size: 0x40000000.
[MT6357] 1 2,37

[CH0][RK0][2666][CBT] Best CA Vref 8, Window Min 51 at CA4, Window Sum 318

[CH0][RK1][2666][CBT] Best CA Vref 8, Window Min 51 at CA4, Window Sum 321

[CH0][RK0][2666][TX] Best Vref 10, Window Min 24 at DQ13, Window Sum 420

[CH0][RK0][2666][RX] Best Vref 13, Window Min 36 at DQ0, Window Sum 613
Byte0 end_step=26  best_step=23 Final TX OE(2T, 0.5T) = (2, 7)
Byte1 end_step=25  best_step=22 Final TX OE(2T, 0.5T) = (2, 6)

[CH0][RK1][2666][TX] Best Vref 12, Window Min 25 at DQ3, Window Sum 421
Byte0 end_step=26  best_step=23 Final TX OE(2T, 0.5T) = (2, 7)
Byte1 end_step=25  best_step=22 Final TX OE(2T, 0.5T) = (2, 6)

[CH1][RK0][2666][CBT] Best CA Vref 8, Window Min 50 at CA4, Window Sum 324

[CH1][RK1][2666][CBT] Best CA Vref 8, Window Min 50 at CA4, Window Sum 323

[CH1][RK0][2666][TX] Best Vref 10, Window Min 24 at DQ6, Window Sum 419

[CH1][RK0][2666][RX] Best Vref 12, Window Min 36 at DQ6, Window Sum 601
Byte0 end_step=26  best_step=23 Final TX OE(2T, 0.5T) = (2, 7)
Byte1 end_step=25  best_step=22 Final TX OE(2T, 0.5T) = (2, 6)

[CH1][RK1][2666][TX] Best Vref 8, Window Min 24 at DQ6, Window Sum 413
Byte0 end_step=26  best_step=23 Final TX OE(2T, 0.5T) = (2, 7)
Byte1 end_step=26  best_step=23 Final TX OE(2T, 0.5T) = (2, 7)


[Calibration Summary] Freqency 1333
CH 0, Rank 0
All Pass.
CH 0, Rank 1
All Pass.
CH 1, Rank 0
All Pass.
CH 1, Rank 1
All Pass.
[MT6357] 1 2,45

[CH0][RK0][3200][CBT] Best CA Vref 8, Window Min 50 at CA4, Window Sum 313

[CH0][RK1][3200][CBT] Best CA Vref 8, Window Min 50 at CA4, Window Sum 320

[CH0][RK0][3200][TX] Best Vref 12, Window Min 21 at DQ13, Window Sum 368

[CH0][RK0][3200][RX] Best Vref 12, Window Min 32 at DQ4, Window Sum 545
Byte0 end_step=30  best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
Byte1 end_step=30  best_step=27 Final TX OE(2T, 0.5T) = (3, 3)

[CH0][RK1][3200][TX] Best Vref 10, Window Min 20 at DQ14, Window Sum 371
Byte0 end_step=30  best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
Byte1 end_step=30  best_step=27 Final TX OE(2T, 0.5T) = (3, 3)

[CH1][RK0][3200][CBT] Best CA Vref 8, Window Min 50 at CA4, Window Sum 331

[CH1][RK1][3200][CBT] Best CA Vref 8, Window Min 50 at CA4, Window Sum 328

[CH1][RK0][3200][TX] Best Vref 10, Window Min 22 at DQ3, Window Sum 368

[CH1][RK0][3200][RX] Best Vref 12, Window Min 31 at DQ3, Window Sum 515
Byte0 end_step=30  best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
Byte1 end_step=30  best_step=27 Final TX OE(2T, 0.5T) = (3, 3)

[CH1][RK1][3200][TX] Best Vref 12, Window Min 20 at DQ14, Window Sum 366
Byte0 end_step=30  best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
Byte1 end_step=30  best_step=27 Final TX OE(2T, 0.5T) = (3, 3)


[Calibration Summary] Freqency 1600
CH 0, Rank 0
All Pass.
CH 0, Rank 1
All Pass.
CH 1, Rank 0
All Pass.
CH 1, Rank 1
All Pass.
final ma_type:2
final ma_type:2


[DRAM_CHECK] result = 0

[switch_dramc_voltage_to_auto_mode]switch dram voltage to auto mode done!!!

base init: MT8365 platform
NOTICE:  BL2: Booting BL31
NOTICE:  BL31: v2.6(release):ea4af38bb-dirty
NOTICE:  BL31: Built : 10:45:31, Jul  8 2022
...
���J
    JJj �D��.38��       +

                         "��J*+CFJw�?�#g"8�[*�*�2(���.*W?       �)fV&�bw��N�!6B*+�B� P(*/                                                                                             �w�wB��ֆ���������ׂ�R�����J�jB����jV����g��O��^�zʆ�����C�J�B��O����K&B����C�kzB���~B��ϬB�f�v�w�B��B��[�Z������ZC����ZC�����B��ƬB����Z�ެ`ZwP��JʴB���N��ެ�B�O��J��Zc��N�Z��ެ�Z�O��J�Z����N�ZF��J�  ���φ����������G��o�_�Ə�����B����O����[K&B^��[r~fB�_�����F������   ���������������g������FڝK�j �����߆�������w�wB�W����Fڎ��z�ڥnjr��Oz�r����OB�r���z���"BO^�Bw���w�����������F����wB�����z����w���V��BB����F��^�J���V�����Q"b�V��      �������Kj����R~��Z�BS���        ���[B~fB����[B~fz����Kc~�B���KB~fB����GV"B���[C�����[C�������ƄkV��ׂ�����������Z���b�������dž��FvB�w�oBg�W�Bg�������b
        ��v�������w��KZ��Jk��B���F�������^���^���O�~B�����o��^�~���������W��K��W�׆k��B�K�_W���Z�K�_W��Ҵ�j���džj���N�k�[b_~b��o��BZJ��N�K�[b_�BKFNWJk�[b_�B�����B����B�k���{�B����O�K�B����O�K�B����O��B����O��B����O�K�Bۯ���O�K�B����O�k�Bۯ���O��B�k�_W���B����O�j�B���̞OB����B�r��B������B���B�Z�Z���B����ZN���NߎjN�C���B�����Bk�b��RC_v����Bk��B�����     ��C��~RW�����   WqFk��B��kB�����B�kN{��B�kN��w��B�kN��Bs����BO�o�ZO��nsrO���JO���JN�BO����BO�ƽ���B�G��f�Z�����(������B���B����B�g_�f>R����?Z������B����B�Kf��w��B�Kf��>j�Kf�����B�Kf�N�NNJ�B�Kf��jB�BP>rf���B�Kf��~��Kf����rB�Kf����B�GV��S��vBSBP>RSB���~o�B������B��B�J��B�����B�k����Bsk����׾�B��O���k߯K�Bg����������B�[F�j���Bgg����B��Ƈ��B�b�K�KjB�����'����B�����B[�Z����B��B������BZ�O~B����B��j�B�J�_W���B�k���{�B��WK��n��B��K_W���B��N_W���B���K��n��B�[����B�KNV�����B�[v�J�BGJ���BGo��jB�k�^J����(��vB�k�^K���cBsk�^J����(�k�^K����B��_N�w�B��_N_W���B�_N�w�B��_N_W���B�wN��W�B��wN��n��B��wK��W�B�wK��n��BGJ��J�BGJ��G�N�B�[v����ZGJ�W���B�[vJ�J�B�[vJ�J�B�[vJ�J�B�[v����GsBGJ��^��dž��B�[vVGB��&z���B�����B�rr�jB�r�cgB�������B�[�J�W��F�[Ղ����>R��Bb�B�r�SgB�vjSgB�FjSל�B������OwVB�V���k�B���B���zB�G���B���V��B�����B���NJ�ǗB��z�W���G�q��WOwW��� G��O��_��O�B���W�`8�ZcB���Z�B�����B������B������B��g��[���o��B��g�V[�o���B��gϯ�[�oϯ�B��g��[�o��B��g�g�[�o      ��B�������O�[��?�r?�O�B�������O�[������O�B�����[�o�w�B�����[���o��B���w�[���ow�B����[�o��B�������[����������B�����[���o����B�����[������B������[�������B����V�[�������B������[����_��B������[����_R�B�����[����_�B�������[��������B������[��������B�����[������B�������[����~���B�����B�o��sB��N���B�o���sB�����B�ov�sB��������g׎�B����G�B�og��B������B�o��sB�����B�o��sB�����B�o��sB�����B�o��sB�W�{B����B�o�sB���g��B�o�Q�sB����G�Ɲ�����B�f���Nw��B�����B�o�sB�����B�o��sB����w���B�o�r��sB������B�o���sBϭ�vB����[�����B�����[�o���B��N���[�o����B�����[�ov��B����G[���g��B������[�g��v�B������B�����[��g���B�����[��o��[�g���[�g���[��g�Q��[��g���[�g�w���B�o��sB�o��sBڭ�bǝ�B�o���sB�o���sB�B���OwVo��s[�o��[�o���[�o���[�g����[�g���B�o���sB��������B�ogs[�g����[�gg�B�o���s[�g�v��[�o����B�osB�o�sB�o���s[�g1���[�o�[�o��B�o4����sB�o��s[�o��B�o��r�B�o��s[��������[�g���B�o��sB�oֆsB�o��s[�g���[�g���[�g��r�B�o��s[�g��[������[�o��BWo���BSo��FK�PzB�����B����BgN����B�KV�>B��v[�g���B�o���s[�o�σ�[�g����B��jB���Əjb���>B�b^�B����B�j^�B�J��j����B�ʏ�O��B�������B����v�_>B���Nb�B���NZ�����v�_�B��wJ�~B���Nz�B���v_N���N��(���NB�B���vv>����NZN[���Nj(���NB>b���N��B���NB(���Nz�Z���NB�B���NJ�B���NJ�B���Nj~B���NҞK��b�Jj�k��b�Jvs���b�JR�B��b�JڞB��b�JbNK��b�Jj�B���^��B����^��B�������B�����B�����B���ϵ�B���ϵ�B��ϵ�B��ϵ�B���ϵ�[�����B���ϵ�B���ϵ�B���ϵ�B���ϵ�B���ϵ�B���ϵ{B��ϵ{B��ϵ{B���ϵ{B��ϵ{B���ϵ{B�og��s[z9o�Q���B�o�sB������OĮ�[�o��[�g���O�B�o���s[�������R�b�f��[�g�����[����~����[�o���[�������[��׌?      ��[�ow�[���g��[��gb���B�o�s[�g���[�g��[�ow�[���o>�[:���v�B�o����B�o�s[�̟���B�ob�n�[������B�o���sB�o���#B�o�s[������B�oF�sB�oO�s[����[���b�n�[�g����[�g��v�[�o���B�o�sB�o��B�o���[�����[�����[�oq��B�o��s[����[�̷��[������[�����B�o�gs[����[����[����g�[����B�o��[������[���F��[����B�o���sB�o�sB�o���[������[�������B�o�s[�����[�o�[�o���k�B�o/gs[�������[��������[������B�oG�s[
                                                                                                                                                  ����[�gG��[���g�[�����[����_[�o��[�gO��B�o��s[�����B�o�s[�g��B�o��sB�o�s[����[�����[������B�o�s[�g��BBBBBB*BbCBBGBbBBBRBBbBC jgcf�CBRƳ�J�CRFBbZ[j�J�^"B�ZWR����~�^~ 0BBBB��"����Z�F��Ƨ�������w���������������Z�F��Ƨ�������w����������������ZoO��Ƨ�������w���������������Z�F��Ƨ�������w����������������Z�F��Ƨ�������w���������������ZoO��Ƨ�������w����������������ZoO��Ƨ�������w���������������ZoO��Ƨ�������w����������������ZoO��Ƨ�������w���������������Z�F��Ƨ�������w����������������Z�F��Ƨ�������w���������������Z�F��Ƨ�������w�����������������ZoO��Ƨ�������w���������������Z�F��Ƨ�������w����������������ZoO��Ƨ�������w���������������ZoO��Ƨ�������w����������������Z�F��Ƨ�������w���������������Z�F��Ƨ�������w���������������
F0: 102B 0000
F3: 1006 0033 [0200]
F3: 4001 00E0 [0200]
F3: 0000 0000
V0: 0000 0000 [0001]
00: 0000 0000
BP: 0C00 0241 [0000]
G0: 1190 0000
EC: 0000 0000 [0001]
T0: 0000 0156 [000F]
Jump to BL

NOTICE:  BL2: v2.6(release):ea4af38bb-dirty
NOTICE:  BL2: Built : 10:45:31, Jul  8 2022
Pll init start...
INFRA_BUS_DCM_CTRL 5f7fe0
before: WDT_SWSYSRST = 0x8000
after: WDT_SWSYSRST = 0x9000
Pll init Done!
[PWRAP] si_en_sel = 0, si_ck_sel = 0, si_sample_ctrl = 0, rdata = 96a9
[PWRAP] si_en_sel = 0, si_ck_sel = 1, si_sample_ctrl = 20, rdata = 5aa5, Pass
[PWRAP] InitSiStrobe (7, 7, 4804) Data Boundary Is Found !!
[PWRAP] SI Strobe Calibration For PMIC 0 Done, (40, 7)
[PWRAP] Read Test pass, return_value=0x0
[PWRAP] Write Test pass
[PWRAP] RECORD_CMD0:  0x0 (Last one command addr)
[PWRAP] RECORD_WDATA0:0x0 (Last one command wdata)
[PWRAP] RECORD_CMD1:  0x0 (Last second command addr)
[PWRAP] RECORD_WDATA1:0x0 (Last second command wdata)
[PWRAP] RECORD_CMD2:  0x0 (Last third command addr)
[PWRAP] RECORD_WDATA2:0x0 (Last third command wdata)
[I2C] Init done
[PMIC]Start
[PMIC]MT6357 CHIP Code = 0x57, mrv=1
[PMIC]POWER_HOLD :0x1
[PMIC]TOP_RST_STATUS[0x152]=0x0
[PMIC]PONSTS[0xc]=0x4
[PMIC]POFFSTS[0xe]=0x0
[PMIC]PGSTATUS0[0x14]=0xfffe
[PMIC]PSOCSTATUS[0x16]=0x0
[PMIC]BUCK_OC_SDN_STATUS[0x1434]=0x0
[PMIC]BUCK_OC_SDN_EN[0x1444]=0x1d1f
[PMIC]THERMALSTATUS[0x18]=0x0
[PMIC]STRUP_CON4[0xa1c]=0x0
[PMIC]TOP_RST_MISC[0x14c]=0x200
[PMIC]TOP_CLK_TRIM[0x38e]=0x6ac0
latch VPROC 800000 uV
latch VSRAM_PROC 900000 uV
latch VSRAM_OTHERS 900000 uV
latch VCORE 800000 uV
latch VMODEM 800000 uV
[pmic_check_rst] PORSTB
[PMIC]just_rst = 0
No EFUSE SW Load
[PMIC]pmic_wdt_set Reg[0x14c]=0x221
[rt5738_driver_probe]
[update_rt5738_chip_id] 0x0, 0x0, 0x0
[rt5738_hw_component_detect] ret 1, PGOOD 0x1
[rt5738_hw_component_detect] mt6691_vdd2(0) exist = 1, Chip ID = 0
mt6691_vdd2_hw_init
[0x0]=0xa5 [0x1]=0xa5 [0x2]=0x92 [0x3]=0x0 [0x4]=0x0 [0x5]=0x81 [0x6]=0x63
[rt5738_driver_probe] PL g_rt5738_0_hw_exist=1, g_rt5738_driver_ready=1
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[update_rt5738_chip_id] 0x0, 0x0, 0x0
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[rt5738_hw_component_detect] ret 0, PGOOD 0x0
[rt5738_hw_component_detect] mt6691_vddq(1) exist = 0, Chip ID = 0
[rt5738_driver_probe] PL mt6691_vddq is not exist
[I2C] id=0,addr: 54, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a8,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[I2C] id=0,addr: 54, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a8,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[update_rt5738_chip_id] 0x0, 0x0, 0x0
[I2C] id=0,addr: 54, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a8,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[rt5738_hw_component_detect] ret 0, PGOOD 0x0
[rt5738_hw_component_detect] ma5748_vdd(2) exist = 0, Chip ID = 0
[rt5738_driver_probe] PL ma5748_vdd is not exist
[hl7593_driver_probe]
[hl7593_read_interface] Reg[3]=0x0
[hl7593_read_interface] val=0x0
[hl7593_read_interface] Reg[4]=0x0
[hl7593_read_interface] val=0x0
[update_hl7593_chip_id] 0x0, 0x0, 0x0
[hl7593_read_interface] Reg[5]=0x81
[hl7593_read_interface] val=0x1
PGOOD = 1, chip_id = 0
[hl7593_hw_component_detect] exist = 0, Chip ID = 0
[hl7593_driver_probe] PL hl7593_vdd2 is not exist
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[hl7593_read_interface] Reg[3]=0x3
[hl7593_read_interface] val=0x3
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[hl7593_read_interface] Reg[4]=0x4
[hl7593_read_interface] val=0x4
[update_hl7593_chip_id] 0x3, 0x4, 0x304
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[hl7593_read_interface] Reg[5]=0x5
[hl7593_read_interface] val=0x0
PGOOD = 0, chip_id = 772
[hl7593_hw_component_detect] exist = 0, Chip ID = 304
[hl7593_driver_probe] PL hl7593_vddq is not exist
[fan53526_driver_probe]
[I2C] id=0,addr: 60, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=c0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[I2C] id=0,addr: 60, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=c0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[update_fan53526_chip_id] 0x3, 0x4, 0x304
[I2C] id=0,addr: 60, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=c0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[fan53526_hw_component_detect] exist = 0, Chip ID = 304
[fan53526_driver_probe] PL fan53526_vdd2 is not exist
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[update_fan53526_chip_id] 0x3, 0x4, 0x304
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[fan53526_hw_component_detect] exist = 0, Chip ID = 304
[fan53526_driver_probe] PL fan53526_vddq is not exist
register vs1 OK
register vmodem OK
register vcore OK
register vproc OK
register vpa OK
register vsram_others OK
register vsram_proc OK
register vdram OK
register vfe28 OK
register vefuse OK
[PMIC]Init done
init_dram:1723: init_dram Starting
Fanning new driver,dram type 3
[MT6357] 1 2,25
[RankNumberDetection] 2

[CH0][RK0][1600][CBT] Best CA Vref 10, Window Min 59 at CA4, Window Sum 358

[CH0][RK1][1600][CBT] Best CA Vref 8, Window Min 59 at CA4, Window Sum 361

[CH0][RK0][1600][TX] Best Vref 12, Window Min 27 at DQ1, Window Sum 440

[CH0][RK0][1600][RX] Best Vref 28, Window Min 56 at DQ7, Window Sum 918
Byte0 end_step=17  best_step=14 Final TX OE(2T, 0.5T) = (1, 6)
Byte1 end_step=17  best_step=14 Final TX OE(2T, 0.5T) = (1, 6)

[CH0][RK1][1600][TX] Best Vref 15, Window Min 27 at DQ1, Window Sum 443
Byte0 end_step=17  best_step=14 Final TX OE(2T, 0.5T) = (1, 6)
Byte1 end_step=17  best_step=14 Final TX OE(2T, 0.5T) = (1, 6)

[CH1][RK0][1600][CBT] Best CA Vref 8, Window Min 56 at CA4, Window Sum 352

[CH1][RK1][1600][CBT] Best CA Vref 8, Window Min 56 at CA4, Window Sum 349

[CH1][RK0][1600][TX] Best Vref 11, Window Min 27 at DQ0, Window Sum 444

[CH1][RK0][1600][RX] Best Vref 28, Window Min 54 at DQ8, Window Sum 908
Byte0 end_step=17  best_step=14 Final TX OE(2T, 0.5T) = (1, 6)
Byte1 end_step=17  best_step=14 Final TX OE(2T, 0.5T) = (1, 6)

[CH1][RK1][1600][TX] Best Vref 16, Window Min 27 at DQ6, Window Sum 442
Byte0 end_step=17  best_step=14 Final TX OE(2T, 0.5T) = (1, 6)
Byte1 end_step=17  best_step=14 Final TX OE(2T, 0.5T) = (1, 6)


[Calibration Summary] Freqency 800
CH 0, Rank 0
All Pass.
CH 0, Rank 1
All Pass.
CH 1, Rank 0
All Pass.
CH 1, Rank 1
All Pass.
CH0, RK0, Rank Size: 0x40000000.
CH1, RK0, Rank Size: 0x40000000.
CH0, RK1, Rank Size: 0x40000000.
CH1, RK1, Rank Size: 0x40000000.
[MT6357] 1 2,37

[CH0][RK0][2666][CBT] Best CA Vref 8, Window Min 51 at CA4, Window Sum 318

[CH0][RK1][2666][CBT] Best CA Vref 8, Window Min 51 at CA4, Window Sum 323

[CH0][RK0][2666][TX] Best Vref 10, Window Min 25 at DQ12, Window Sum 422

[CH0][RK0][2666][RX] Best Vref 13, Window Min 36 at DQ0, Window Sum 610
Byte0 end_step=26  best_step=23 Final TX OE(2T, 0.5T) = (2, 7)
Byte1 end_step=25  best_step=22 Final TX OE(2T, 0.5T) = (2, 6)

[CH0][RK1][2666][TX] Best Vref 10, Window Min 25 at DQ6, Window Sum 426
Byte0 end_step=26  best_step=23 Final TX OE(2T, 0.5T) = (2, 7)
Byte1 end_step=25  best_step=22 Final TX OE(2T, 0.5T) = (2, 6)

[CH1][RK0][2666][CBT] Best CA Vref 8, Window Min 50 at CA4, Window Sum 324

[CH1][RK1][2666][CBT] Best CA Vref 8, Window Min 50 at CA4, Window Sum 322

[CH1][RK0][2666][TX] Best Vref 10, Window Min 24 at DQ13, Window Sum 417

[CH1][RK0][2666][RX] Best Vref 12, Window Min 36 at DQ6, Window Sum 599
Byte0 end_step=26  best_step=23 Final TX OE(2T, 0.5T) = (2, 7)
Byte1 end_step=26  best_step=23 Final TX OE(2T, 0.5T) = (2, 7)

[CH1][RK1][2666][TX] Best Vref 10, Window Min 24 at DQ6, Window Sum 415
Byte0 end_step=26  best_step=23 Final TX OE(2T, 0.5T) = (2, 7)
Byte1 end_step=26  best_step=23 Final TX OE(2T, 0.5T) = (2, 7)


[Calibration Summary] Freqency 1333
CH 0, Rank 0
All Pass.
CH 0, Rank 1
All Pass.
CH 1, Rank 0
All Pass.
CH 1, Rank 1
All Pass.
[MT6357] 1 2,45

[CH0][RK0][3200][CBT] Best CA Vref 8, Window Min 50 at CA4, Window Sum 313

[CH0][RK1][3200][CBT] Best CA Vref 8, Window Min 50 at CA4, Window Sum 320

[CH0][RK0][3200][TX] Best Vref 10, Window Min 20 at DQ13, Window Sum 368

[CH0][RK0][3200][RX] Best Vref 12, Window Min 32 at DQ4, Window Sum 550
Byte0 end_step=30  best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
Byte1 end_step=30  best_step=27 Final TX OE(2T, 0.5T) = (3, 3)

[CH0][RK1][3200][TX] Best Vref 10, Window Min 20 at DQ13, Window Sum 372
Byte0 end_step=30  best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
Byte1 end_step=30  best_step=27 Final TX OE(2T, 0.5T) = (3, 3)

[CH1][RK0][3200][CBT] Best CA Vref 8, Window Min 50 at CA4, Window Sum 330

[CH1][RK1][3200][CBT] Best CA Vref 8, Window Min 50 at CA4, Window Sum 329

[CH1][RK0][3200][TX] Best Vref 12, Window Min 22 at DQ3, Window Sum 364

[CH1][RK0][3200][RX] Best Vref 12, Window Min 31 at DQ3, Window Sum 515
Byte0 end_step=30  best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
Byte1 end_step=30  best_step=27 Final TX OE(2T, 0.5T) = (3, 3)

[CH1][RK1][3200][TX] Best Vref 12, Window Min 21 at DQ7, Window Sum 363
Byte0 end_step=30  best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
Byte1 end_step=30  best_step=27 Final TX OE(2T, 0.5T) = (3, 3)


[Calibration Summary] Freqency 1600
CH 0, Rank 0
All Pass.
CH 0, Rank 1
All Pass.
CH 1, Rank 0
All Pass.
CH 1, Rank 1
All Pass.
final ma_type:2
final ma_type:2


[DRAM_CHECK] result = 0

[switch_dramc_voltage_to_auto_mode]switch dram voltage to auto mode done!!!

base init: MT8365 platform
NOTICE:  BL2: Booting BL31
NOTICE:  BL31: v2.6(release):ea4af38bb-dirty
NOTICE:  BL31: Built : 10:45:31, Jul  8 2022
...
��*JJj /t��83>/���(
                  "���&�JJKCFJ7���8����'8����V���&VW�w(�W?      q'��8&�C�w�     n!Jb�)()        �
                                                                                                 "��B�)
                                                                                                       N+�+)�9"�v��wJjW?.�g�6   "��*�7
                                                                                                                                      c
                                                                                                                                       ++�O�B0�],R "�g*2%E+:��v��w(W?wn�W�>֠C�8���wJ�w2>�mBF� �/l0"�OFJ�wSGJ������V����:F(
ʌ�&JF��NJB�F����ʆ���F�JJJʆ�f҆�����G�NJ����v�OJwqG�wB��ֆ����������B�R�����J�jB����jV���gτ��O��^�z�����C�J�B��O����Kf����C�kzB���~B��ϬBÏ��v�w�B��B��[[������ZC����ZC��j������ƬB[p��R��ެ�Z�O��JʴB���N�Z�Z�ެ`ZwP��J�Z�O��N�Z��ެ�ZwP��J�Z����N�ZB����      ������Ά������G�o��B�����B��Ʀ��O����[Kf����[r~�B�_��j��������    �������������F����g��NjG��ʝK�jBg�^�G��Fʎ��z�ڥn�jr��Oz�����z�����B�����z���b�O^�Bw����ƴ������G������wB�����z������KZ�V��BB����J��^�J���VD�����[B�V������&J��KJ����R~��Z�BS���      ���[B~fB����[B~�B����Kc~&BK��KB~fB����GV"B[��[C������[C�����Ƅ�V��׆�������������FkS�"B�׆�������dž��FvB��rPoB�ˬ2�B��������b��v�����w�����Jk��B����������^����^��>ZK�O�~B���j�o�z^P~���z��z�W�j�J����Nj���B�K�_W���ZsK�_W��R��j����&jKFNWJk�[b_�B��o��BkFnWJK�[b_�BKFNWJk�[b_�B�����B����B�k���{�B����O�K�B����O�K�Bۯ���O��B����O��B����O�K�B����O�K�B����O�k�B����O��B�k�_W���B����O�j�B���̞OB���B�r��B������B���B�Z�B�n�Bv�~�����N��N�C��BC_v����b���Bj����'��Bk�B�����SqF���B�_�����?J��bR_�BO�kB�����BO�gJ�BO���w��Bs����BO����B�kN�B�kN�n3z�kN��B�kN�JN�B�kN�nBO�ƽ���B�G��f�j����B������B����B�G���B����f~z�����B������B�G���B�Kf��w��B�Kf��~z�Kf�����B�Kf�N�NNJ�B�Kf��jBSBP�B�k��B�Kf��~r�Kf�����B�Kf��R��B�����S��vB�j�^B�B���~o�B������B����J��Bj����B�k���Bsk����׾�B��O���k߯K�B������gq���B�[F�>r���B���G��g����B��Ƈ��B�b�K�KjB�����Gk����B�����B[�Z����B��B������B��O~B����B��j�B��J�_W���Bsk���{�B��WK��n��B��K_W���B���N_W���B��K��n��B�KN���B�KNV�����BGJ��J�B�J���B��vBGo��jB�k�^J����B�k�^K���c��k�^J����B�k�^K����B��_N�w�B��_N_W���B��_N�w�B��_N_W���B�wN��W�B��wN��n��B��wK��W�B��wK��n��B�J��J�B�[v�G�N�B�[v����zGJ�W���B�[vJ�J�BGJ��J�B�[vJ�J�BGJ�����GsBGJ��^��dž��B�[vVGB�^B���B���zB�G��B�rr�jB�r�cgB��W���SƞjC[�z�W��ZoS{B�����B��Bb�B�r�SgB�vjSgB�FjSל�z�BoO��Ƨ�������w����������������Bڜ���B�����B�����BC�����OwVB������מ��FBڜ���B������OwVB����B����������OwVB������OwV������q�v�g$���b����R������k���R����[����C������Bj��B[BBBBB�B�BBp�O�����W�����Cj�j�J��O��B�vBBB���RB�B�BBp�J�������R�B��[����C��~�׭וJ��B[BBBBB�B�BBp�O�����W����Cj�jjJz W�KBBB�w��B�B�BBp�J�������R�B��[����C������וJ��BKBBBBB�B�BBp�O�����WǏ���Cj�jjJz[�ҿ�BB�BBB�w�zBB�BBB�p�J���8���zBB����&��J������OwVJ���J���z��?s��~�k��Z��vŭ�ŭ�Z������OwVŭ���Ư���k��k���΅b���k�����Kv{����Gv{�����G�Z�����g��������J�����J���
F0: 102B 0000
F3: 1006 0033 [0200]
F3: 4001 00E0 [0200]
F3: 0000 0000
V0: 0000 0000 [0001]
00: 0000 0000
BP: 0C00 0241 [0000]
G0: 1190 0000
EC: 0000 0000 [0001]
T0: 0000 010F [000F]
Jump to BL

NOTICE:  BL2: v2.6(release):ea4af38bb-dirty
NOTICE:  BL2: Built : 10:45:31, Jul  8 2022
Pll init start...
INFRA_BUS_DCM_CTRL 5f7fe0
before: WDT_SWSYSRST = 0x8000
after: WDT_SWSYSRST = 0x9000
Pll init Done!
[PWRAP] si_en_sel = 0, si_ck_sel = 0, si_sample_ctrl = 0, rdata = 96a9
[PWRAP] si_en_sel = 0, si_ck_sel = 1, si_sample_ctrl = 20, rdata = 5aa5, Pass
[PWRAP] InitSiStrobe (7, 7, 4804) Data Boundary Is Found !!
[PWRAP] SI Strobe Calibration For PMIC 0 Done, (40, 7)
[PWRAP] Read Test pass, return_value=0x0
[PWRAP] Write Test pass
[PWRAP] RECORD_CMD0:  0x14aa (Last one command addr)
[PWRAP] RECORD_WDATA0:0x2d (Last one command wdata)
[PWRAP] RECORD_CMD1:  0x19fa (Last second command addr)
[PWRAP] RECORD_WDATA1:0x3d (Last second command wdata)
[PWRAP] RECORD_CMD2:  0x19fa (Last third command addr)
[PWRAP] RECORD_WDATA2:0x39 (Last third command wdata)
[I2C] Init done
[PMIC]Start
[PMIC]MT6357 CHIP Code = 0x57, mrv=1
[PMIC]POWER_HOLD :0x1
[PMIC]TOP_RST_STATUS[0x152]=0x48
[PMIC]PONSTS[0xc]=0x0
[PMIC]POFFSTS[0xe]=0x400
[PMIC]PGSTATUS0[0x14]=0xfffe
[PMIC]PSOCSTATUS[0x16]=0x0
[PMIC]BUCK_OC_SDN_STATUS[0x1434]=0x0
[PMIC]BUCK_OC_SDN_EN[0x1444]=0x1d1f
[PMIC]THERMALSTATUS[0x18]=0x0
[PMIC]STRUP_CON4[0xa1c]=0x0
[PMIC]TOP_RST_MISC[0x14c]=0x204
[PMIC]TOP_CLK_TRIM[0x38e]=0x6ac0
latch VPROC 800000 uV
latch VSRAM_PROC 900000 uV
latch VSRAM_OTHERS 900000 uV
latch VCORE 800000 uV
latch VMODEM 500000 uV
[pmic_check_rst] DDLO_RSTB
[pmic_check_rst] AP Watchdog
[PMIC]just_rst = 0
No EFUSE SW Load
[PMIC]pmic_wdt_set Reg[0x14c]=0x225
[rt5738_driver_probe]
[update_rt5738_chip_id] 0x0, 0x0, 0x0
[rt5738_hw_component_detect] ret 1, PGOOD 0x1
[rt5738_hw_component_detect] mt6691_vdd2(0) exist = 1, Chip ID = 0
mt6691_vdd2_hw_init
[0x0]=0xa5 [0x1]=0xa5 [0x2]=0x92 [0x3]=0x0 [0x4]=0x0 [0x5]=0x81 [0x6]=0x63
[rt5738_driver_probe] PL g_rt5738_0_hw_exist=1, g_rt5738_driver_ready=1
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[update_rt5738_chip_id] 0x0, 0x0, 0x0
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[rt5738_hw_component_detect] ret 0, PGOOD 0x0
[rt5738_hw_component_detect] mt6691_vddq(1) exist = 0, Chip ID = 0
[rt5738_driver_probe] PL mt6691_vddq is not exist
[I2C] id=0,addr: 54, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a8,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[I2C] id=0,addr: 54, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a8,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[update_rt5738_chip_id] 0x0, 0x0, 0x0
[I2C] id=0,addr: 54, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a8,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[rt5738_hw_component_detect] ret 0, PGOOD 0x0
[rt5738_hw_component_detect] ma5748_vdd(2) exist = 0, Chip ID = 0
[rt5738_driver_probe] PL ma5748_vdd is not exist
[hl7593_driver_probe]
[hl7593_read_interface] Reg[3]=0x0
[hl7593_read_interface] val=0x0
[hl7593_read_interface] Reg[4]=0x0
[hl7593_read_interface] val=0x0
[update_hl7593_chip_id] 0x0, 0x0, 0x0
[hl7593_read_interface] Reg[5]=0x81
[hl7593_read_interface] val=0x1
PGOOD = 1, chip_id = 0
[hl7593_hw_component_detect] exist = 0, Chip ID = 0
[hl7593_driver_probe] PL hl7593_vdd2 is not exist
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[hl7593_read_interface] Reg[3]=0x3
[hl7593_read_interface] val=0x3
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[hl7593_read_interface] Reg[4]=0x4
[hl7593_read_interface] val=0x4
[update_hl7593_chip_id] 0x3, 0x4, 0x304
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[hl7593_read_interface] Reg[5]=0x5
[hl7593_read_interface] val=0x0
PGOOD = 0, chip_id = 772
[hl7593_hw_component_detect] exist = 0, Chip ID = 304
[hl7593_driver_probe] PL hl7593_vddq is not exist
[fan53526_driver_probe]
[I2C] id=0,addr: 60, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=c0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[I2C] id=0,addr: 60, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=c0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[update_fan53526_chip_id] 0x3, 0x4, 0x304
[I2C] id=0,addr: 60, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=c0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[fan53526_hw_component_detect] exist = 0, Chip ID = 304
[fan53526_driver_probe] PL fan53526_vdd2 is not exist
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[update_fan53526_chip_id] 0x3, 0x4, 0x304
[I2C] id=0,addr: 50, transfer error
[I2C] I2C_ACKERR
[I2C] I2C structure:
[I2C] Id=0,Dma_en=0,Auto_restart=0,Poll_en=1,Op=3
[I2C] Irq_stat=3,source_clk=124800,clk_div=5,speed=100
[I2C] base address 0x11007000
[I2C] I2C register:
[I2C] SLAVE_ADDR=a0,INTR_MASK=f8,INTR_STAT=3,CONTROL=3a
[I2C] TRANSFER_LEN=1,TRANSAC_LEN=2,DELAY_LEN=2
[I2C] TIMING=418,START=0,FIFO_STAT=841,IO_CONFIG=3,HS=0
[I2C] DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001
[I2C] TRANSFER_LEN_AUX=1,FIFO_THRESH=f00,RSV_DEBUG=0
[I2C] DEBUGCTRL=0,CLOCK_DIV=4,SCL_HL_RATIO=c3
[I2C] SCL_HS_HL_RATIO=41,SCL_MIS_COMP_POINT=0
[I2C] STA_STOP_AC_TIME=0,HS_STA_STOP_AC_TIME=0
[I2C] DATA_TIME=0,TIME_OUT=0
[I2C] i2c_write_read fails(-121).
[fan53526_hw_component_detect] exist = 0, Chip ID = 304
[fan53526_driver_probe] PL fan53526_vddq is not exist
register vs1 OK
register vmodem OK
register vcore OK
register vproc OK
register vpa OK
register vsram_others OK
register vsram_proc OK
register vdram OK
register vfe28 OK
register vefuse OK
[PMIC]Init done
init_dram:1723: init_dram Starting
Fanning new driver,dram type 3
[MT6357] 1 2,25
[RankNumberDetection] 2

[CH0][RK0][1600][CBT] Best CA Vref 8, Window Min 59 at CA4, Window Sum 357

[CH0][RK1][1600][CBT] Best CA Vref 8, Window Min 59 at CA4, Window Sum 363

[CH0][RK0][1600][TX] Best Vref 14, Window Min 27 at DQ1, Window Sum 444

[CH0][RK0][1600][RX] Best Vref 30, Window Min 55 at DQ10, Window Sum 906
Byte0 end_step=17  best_step=14 Final TX OE(2T, 0.5T) = (1, 6)
Byte1 end_step=17  best_step=14 Final TX OE(2T, 0.5T) = (1, 6)

[CH0][RK1][1600][TX] Best Vref 13, Window Min 27 at DQ1, Window Sum 446
Byte0 end_step=17  best_step=14 Final TX OE(2T, 0.5T) = (1, 6)
Byte1 end_step=17  best_step=14 Final TX OE(2T, 0.5T) = (1, 6)

[CH1][RK0][1600][CBT] Best CA Vref 8, Window Min 56 at CA4, Window Sum 351

[CH1][RK1][1600][CBT] Best CA Vref 8, Window Min 56 at CA4, Window Sum 349

[CH1][RK0][1600][TX] Best Vref 13, Window Min 27 at DQ0, Window Sum 439

[CH1][RK0][1600][RX] Best Vref 28, Window Min 53 at DQ8, Window Sum 900
Byte0 end_step=17  best_step=14 Final TX OE(2T, 0.5T) = (1, 6)
Byte1 end_step=17  best_step=14 Final TX OE(2T, 0.5T) = (1, 6)

[CH1][RK1][1600][TX] Best Vref 17, Window Min 27 at DQ4, Window Sum 441
Byte0 end_step=17  best_step=14 Final TX OE(2T, 0.5T) = (1, 6)
Byte1 end_step=17  best_step=14 Final TX OE(2T, 0.5T) = (1, 6)


[Calibration Summary] Freqency 800
CH 0, Rank 0
All Pass.
CH 0, Rank 1
All Pass.
CH 1, Rank 0
All Pass.
CH 1, Rank 1
All Pass.
CH0, RK0, Rank Size: 0x40000000.
CH1, RK0, Rank Size: 0x40000000.
CH0, RK1, Rank Size: 0x40000000.
CH1, RK1, Rank Size: 0x40000000.
[MT6357] 1 2,37

[CH0][RK0][2666][CBT] Best CA Vref 8, Window Min 51 at CA4, Window Sum 318

[CH0][RK1][2666][CBT] Best CA Vref 8, Window Min 51 at CA4, Window Sum 321

[CH0][RK0][2666][TX] Best Vref 10, Window Min 24 at DQ13, Window Sum 420

[CH0][RK0][2666][RX] Best Vref 13, Window Min 36 at DQ0, Window Sum 613
Byte0 end_step=26  best_step=23 Final TX OE(2T, 0.5T) = (2, 7)
Byte1 end_step=25  best_step=22 Final TX OE(2T, 0.5T) = (2, 6)

[CH0][RK1][2666][TX] Best Vref 12, Window Min 25 at DQ3, Window Sum 421
Byte0 end_step=26  best_step=23 Final TX OE(2T, 0.5T) = (2, 7)
Byte1 end_step=25  best_step=22 Final TX OE(2T, 0.5T) = (2, 6)

[CH1][RK0][2666][CBT] Best CA Vref 8, Window Min 50 at CA4, Window Sum 324

[CH1][RK1][2666][CBT] Best CA Vref 8, Window Min 50 at CA4, Window Sum 323

[CH1][RK0][2666][TX] Best Vref 10, Window Min 24 at DQ6, Window Sum 419

[CH1][RK0][2666][RX] Best Vref 12, Window Min 36 at DQ6, Window Sum 601
Byte0 end_step=26  best_step=23 Final TX OE(2T, 0.5T) = (2, 7)
Byte1 end_step=25  best_step=22 Final TX OE(2T, 0.5T) = (2, 6)

[CH1][RK1][2666][TX] Best Vref 8, Window Min 24 at DQ6, Window Sum 413
Byte0 end_step=26  best_step=23 Final TX OE(2T, 0.5T) = (2, 7)
Byte1 end_step=26  best_step=23 Final TX OE(2T, 0.5T) = (2, 7)


[Calibration Summary] Freqency 1333
CH 0, Rank 0
All Pass.
CH 0, Rank 1
All Pass.
CH 1, Rank 0
All Pass.
CH 1, Rank 1
All Pass.
[MT6357] 1 2,45

[CH0][RK0][3200][CBT] Best CA Vref 8, Window Min 50 at CA4, Window Sum 313

[CH0][RK1][3200][CBT] Best CA Vref 8, Window Min 50 at CA4, Window Sum 320

[CH0][RK0][3200][TX] Best Vref 12, Window Min 21 at DQ13, Window Sum 368

[CH0][RK0][3200][RX] Best Vref 12, Window Min 32 at DQ4, Window Sum 545
Byte0 end_step=30  best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
Byte1 end_step=30  best_step=27 Final TX OE(2T, 0.5T) = (3, 3)

[CH0][RK1][3200][TX] Best Vref 10, Window Min 20 at DQ14, Window Sum 371
Byte0 end_step=30  best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
Byte1 end_step=30  best_step=27 Final TX OE(2T, 0.5T) = (3, 3)

[CH1][RK0][3200][CBT] Best CA Vref 8, Window Min 50 at CA4, Window Sum 331

[CH1][RK1][3200][CBT] Best CA Vref 8, Window Min 50 at CA4, Window Sum 328

[CH1][RK0][3200][TX] Best Vref 10, Window Min 22 at DQ3, Window Sum 368

[CH1][RK0][3200][RX] Best Vref 12, Window Min 31 at DQ3, Window Sum 515
Byte0 end_step=30  best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
Byte1 end_step=30  best_step=27 Final TX OE(2T, 0.5T) = (3, 3)

[CH1][RK1][3200][TX] Best Vref 12, Window Min 20 at DQ14, Window Sum 366
Byte0 end_step=30  best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
Byte1 end_step=30  best_step=27 Final TX OE(2T, 0.5T) = (3, 3)


[Calibration Summary] Freqency 1600
CH 0, Rank 0
All Pass.
CH 0, Rank 1
All Pass.
CH 1, Rank 0
All Pass.
CH 1, Rank 1
All Pass.
final ma_type:2
final ma_type:2


[DRAM_CHECK] result = 0

[switch_dramc_voltage_to_auto_mode]switch dram voltage to auto mode done!!!

base init: MT8365 platform
NOTICE:  BL2: Booting BL31
NOTICE:  BL31: v2.6(release):ea4af38bb-dirty
NOTICE:  BL31: Built : 10:45:31, Jul  8 2022
...
���J
    JJj �D��.38��       +

                         "��J*+CFJw�?�#g"8�[*�*�2(���.*W?       �)fV&�bw��N�!6B*+�B� P(*/                                                                                             �w�wB��ֆ���������ׂ�R�����J�jB����jV����g��O��^�zʆ�����C�J�B��O����K&B����C�kzB���~B��ϬB�f�v�w�B��B��[�Z������ZC����ZC�����B��ƬB����Z�ެ`ZwP��JʴB���N��ެ�B�O��J��Zc��N�Z��ެ�Z�O��J�Z����N�ZF��J�  ���φ����������G��o�_�Ə�����B����O����[K&B^��[r~fB�_�����F������   ���������������g������FڝK�j �����߆�������w�wB�W����Fڎ��z�ڥnjr��Oz�r����OB�r���z���"BO^�Bw���w�����������F����wB�����z����w���V��BB����F��^�J���V�����Q"b�V��      �������Kj����R~��Z�BS���        ���[B~fB����[B~fz����Kc~�B���KB~fB����GV"B���[C�����[C�������ƄkV��ׂ�����������Z���b�������dž��FvB�w�oBg�W�Bg�������b
        ��v�������w��KZ��Jk��B���F�������^���^���O�~B�����o��^�~���������W��K��W�׆k��B�K�_W���Z�K�_W��Ҵ�j���džj���N�k�[b_~b��o��BZJ��N�K�[b_�BKFNWJk�[b_�B�����B����B�k���{�B����O�K�B����O�K�B����O��B����O��B����O�K�Bۯ���O�K�B����O�k�Bۯ���O��B�k�_W���B����O�j�B���̞OB����B�r��B������B���B�Z�Z���B����ZN���NߎjN�C���B�����Bk�b��RC_v����Bk��B�����     ��C��~RW�����   WqFk��B��kB�����B�kN{��B�kN��w��B�kN��Bs����BO�o�ZO��nsrO���JO���JN�BO����BO�ƽ���B�G��f�Z�����(������B���B����B�g_�f>R����?Z������B����B�Kf��w��B�Kf��>j�Kf�����B�Kf�N�NNJ�B�Kf��jB�BP>rf���B�Kf��~��Kf����rB�Kf����B�GV��S��vBSBP>RSB���~o�B������B��B�J��B�����B�k����Bsk����׾�B��O���k߯K�Bg����������B�[F�j���Bgg����B��Ƈ��B�b�K�KjB�����'����B�����B[�Z����B��B������BZ�O~B����B��j�B�J�_W���B�k���{�B��WK��n��B��K_W���B��N_W���B���K��n��B�[����B�KNV�����B�[v�J�BGJ���BGo��jB�k�^J����(��vB�k�^K���cBsk�^J����(�k�^K����B��_N�w�B��_N_W���B�_N�w�B��_N_W���B�wN��W�B��wN��n��B��wK��W�B�wK��n��BGJ��J�BGJ��G�N�B�[v����ZGJ�W���B�[vJ�J�B�[vJ�J�B�[vJ�J�B�[v����GsBGJ��^��dž��B�[vVGB��&z���B�����B�rr�jB�r�cgB�������B�[�J�W��F�[Ղ����>R��Bb�B�r�SgB�vjSgB�FjSל�B������OwVB�V���k�B���B���zB�G���B���V��B�����B���NJ�ǗB��z�W���G�q��WOwW��� G��O��_��O�B���W�`8�ZcB���Z�B�����B������B������B��g��[���o��B��g�V[�o���B��gϯ�[�oϯ�B��g��[�o��B��g�g�[�o      ��B�������O�[��?�r?�O�B�������O�[������O�B�����[�o�w�B�����[���o��B���w�[���ow�B����[�o��B�������[����������B�����[���o����B�����[������B������[�������B����V�[�������B������[����_��B������[����_R�B�����[����_�B�������[��������B������[��������B�����[������B�������[����~���B�����B�o��sB��N���B�o���sB�����B�ov�sB��������g׎�B����G�B�og��B������B�o��sB�����B�o��sB�����B�o��sB�����B�o��sB�W�{B����B�o�sB���g��B�o�Q�sB����G�Ɲ�����B�f���Nw��B�����B�o�sB�����B�o��sB����w���B�o�r��sB������B�o���sBϭ�vB����[�����B�����[�o���B��N���[�o����B�����[�ov��B����G[���g��B������[�g��v�B������B�����[��g���B�����[��o��[�g���[�g���[��g�Q��[��g���[�g�w���B�o��sB�o��sBڭ�bǝ�B�o���sB�o���sB�B���OwVo��s[�o��[�o���[�o���[�g����[�g���B�o���sB��������B�ogs[�g����[�gg�B�o���s[�g�v��[�o����B�osB�o�sB�o���s[�g1���[�o�[�o��B�o4����sB�o��s[�o��B�o��r�B�o��s[��������[�g���B�o��sB�oֆsB�o��s[�g���[�g���[�g��r�B�o��s[�g��[������[�o��BWo���BSo��FK�PzB�����B����BgN����B�KV�>B��v[�g���B�o���s[�o�σ�[�g����B��jB���Əjb���>B�b^�B����B�j^�B�J��j����B�ʏ�O��B�������B����v�_>B���Nb�B���NZ�����v�_�B��wJ�~B���Nz�B���v_N���N��(���NB�B���vv>����NZN[���Nj(���NB>b���N��B���NB(���Nz�Z���NB�B���NJ�B���NJ�B���Nj~B���NҞK��b�Jj�k��b�Jvs���b�JR�B��b�JڞB��b�JbNK��b�Jj�B���^��B����^��B�������B�����B�����B���ϵ�B���ϵ�B��ϵ�B��ϵ�B���ϵ�[�����B���ϵ�B���ϵ�B���ϵ�B���ϵ�B���ϵ�B���ϵ{B��ϵ{B��ϵ{B���ϵ{B��ϵ{B���ϵ{B�og��s[z9o�Q���B�o�sB������OĮ�[�o��[�g���O�B�o���s[�������R�b�f��[�g�����[����~����[�o���[�������[��׌?      ��[�ow�[���g��[��gb���B�o�s[�g���[�g��[�ow�[���o>�[:���v�B�o����B�o�s[�̟���B�ob�n�[������B�o���sB�o���#B�o�s[������B�oF�sB�oO�s[����[���b�n�[�g����[�g��v�[�o���B�o�sB�o��B�o���[�����[�����[�oq��B�o��s[����[�̷��[������[�����B�o�gs[����[����[����g�[����B�o��[������[���F��[����B�o���sB�o�sB�o���[������[�������B�o�s[�����[�o�[�o���k�B�o/gs[�������[��������[������B�oG�s[
                                                                                                                                                  ����[�gG��[���g�[�����[����_[�o��[�gO��B�o��s[�����B�o�s[�g��B�o��sB�o�s[����[�����[������B�o�s[�g��BBBBBB*BbCBBGBbBBBRBBbBC jgcf�CBRƳ�J�CRFBbZ[j�J�^"B�ZWR����~�^~ 0BBBB��"����Z�F��Ƨ�������w���������������Z�F��Ƨ�������w����������������ZoO��Ƨ�������w���������������Z�F��Ƨ�������w����������������Z�F��Ƨ�������w���������������ZoO��Ƨ�������w����������������ZoO��Ƨ�������w���������������ZoO��Ƨ�������w����������������ZoO��Ƨ�������w���������������Z�F��Ƨ�������w����������������Z�F��Ƨ�������w���������������Z�F��Ƨ�������w�����������������ZoO��Ƨ�������w���������������Z�F��Ƨ�������w����������������ZoO��Ƨ�������w���������������ZoO��Ƨ�������w����������������Z�F��Ƨ�������w���������������Z�F��Ƨ�������w���������������